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Epson Research and Development Page 5
Vancouver Design Center
Interfacing to the NEC VR4181A™ Microprocessor S1D13708
Issue Date: 01/11/05 X39A-G-008-01
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Configuration Options . . . . . . . . . . . . . . . . . . . 13
Table 4-2: CLKI to BCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
List of Figures
Figure 4-1: Typical Implementation of VR4181A to S1D13708 Interface. . . . . . . . . . . . . . .12