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Page 154 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
8.3.10 Extended Registers
bits 16-0 Memory Access Pointer Bits [16:0]
These registers control memory accesses for the Indirect Interface only (CNF[2:0] =
111). These bits contain a pointer to the address position in the display buffer (memory)
used when a “data” read/write is executed. At reset, these registers are set to 0. After each
byte read/write, the Memory Access Pointer is incremented by 1. After each word
read/write, the Memory Access Pointer is incremented by 2. For further information on
accessing the S1D13708 display buffer, see Section 17, “Big-Endian Bus Interface” on
page 212.
Note
1
If the Memory Access Pointer programmed specifies an odd memory address, only
byte accesses may be performed.
2
These bits take effect only after a “command” write to the Memory Access Start
register (REG[C4h]).
bits 7-0 Memory Access Start [7:0]
This register controls memory accesses for the Indirect Interface only (CNF[2:0] =
111). This register is the trigger which readies the interface for reads/writes from/to the
display buffer. After a “command” write to this register, successive reads/writes may be
performed. After each byte read/write, the Memory Access Pointer is incremented by 1.
After each word read/write, the Memory Access Pointer is incremented by 2.
Memory Access Pointer 0
REG[C0h] Read/Write
Memory Access Pointer Bits 7-0
76543210
Memory Access Pointer 1
REG[C1h] Read/Write
Memory Access Pointer Bits 15-8
76543210
Memory Access Pointer 2
REG[C2h] Read/Write
n/a
Memory
Access
Pointer
Bit 16
7 6 5 4 3 2 10
Memory Access Start
REG[C4h] Write only
n/a
7 6 5 4 3 2 1 0