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Page 4 Epson Research and Development
Vancouver Design Center
S1D13708 Power Consumption
X39A-G-006-01 Issue Date: 01/11/25
1.1 Conditions
To illustrate the various factors that can effect power, the following table list the power
consumption for a typical Motorola DragonBall VZ interface implementation. The
DragonBall clock output of 33MHz was the connected to CLKI and divided internally for
BCLK, MCLK and PCLK.
The following table provides an example of some 320x240 and 160x160 panels and the
effects on power consumption in specific environments. The following conditions apply:
• All tests had an appropriate LCD panel connected to the LCD outputs of the S1D13708.
• All tests were run with a static full color palette display.
• All tests were done using the DragonBall host bus interface (CLKI = 33MHz).
1. S1D13708 Power Save Mode enabled, CLKI is active.
2. S1D13708 Power Save Mode enabled, CLKI is inactive with input tied to ground.
Table 1-1: S1D13708 Power Consumption
Test Condition
CORE V
DD
= 1.8V and IO V
DD
= 3.3V
Power Consumption (mA)
S1D13708
Active
Power Save Mode
Resolution
Panel Type
(Color)
Frame
Rate
Clocks (MHz)
Color
Depth
CORE IO CORE
1
IO
1
CORE
2
IO
2
320x240
18-Bit
HR-TFT
84
CLKI= 33MHz
MCLK= BCLK= CLKI
PCLK= CLKI/4
8 1.51 4.13 0.86 0.57 0.56 0.34
4 1.33 3.79 — — — —
2 1.24 3.76 — — — —
1 1.20 3.78 — — — —
18-Bit
TFT
72
CLKI= 33MHz
MCLK= BCLK= CLKI
PCLK= CLKI/4
8 1.52 4.81 — — — —
8-Bit STN
Format 2
93
CLKI= 33MHz
MCLK= BCLK= CLKI
PCLK= CLKI/4
8 1.75 4.17 — — — —
160x160
18-Bit
HR-TFT
93
CLKI= 33MHz
MCLK= BCLK= CLKI
PCLK= CLKI/8
16 1.24 2.83 0.80 0.57 0.51 0.34
8 1.10 2.66 — — — —
4 1.02 2.40 — — — —
2 0.98 2.37 — — — —
1 0.97 2.41 — — — —