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Page 28 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
4.2 Pinout Diagram - Die Form
Table 4-2: S1D13708 Pad Layout
VSS
IOVDD
CNF3
CNF4
CNF5
CNF6
CNF7
TESTEN
GPO0
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
VSS
CLKI2
IOVDD
FPSHIFT
VSS
COREVDD
CVOUT
PWMOUT
GPO0
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
VSS
COREVDD
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
COREVDD
99 65
VSS
VSS
100
S1D13708
64
IOVDD
CNF2
101 87 57 63
GPIO6
CNF1
102 88 56 62
FPLINE
CNF0
103 89 55 61
FPFRAME
FPDAT17
104 90 54 60
*CUT
FPDAT16
105 91 53 59
VSS
FPDAT15
106 92 52 58
IOVDD
FPDAT14
107 93 51 57
WAIT#
FPDAT13
108 94 50 56
RD#
FPDAT12
109 95 49 55
BS#
FPDAT11
110 96 48 54
M/R#
FPDAT10
111 97 47 53
DB0
IOVDD
112 98 46 52
DB1
VSS
113 99 45 51
DB2
FPDAT9
114 100 44 50
DB3
FPDAT8
115 101 43 49
DB4
FPDAT7
116 102 42 48
DB5
FPDAT6
117 103 41 47
DB6
FPDAT5
118 104 40 46
DB7
COREVDD
119 105 39 45
VSS
VSS
120 106 38 44
COREVDD
FPDAT4
121 107 37 43
AB0
FPDAT3
122 108 36 42
AB1
FPDAT2
123 109 35 41
AB2
FPDAT1
124 110 34 40
AB3
FPDAT0
125 111 33 39
AB4
IOVDD
126 112 32 38
AB5
VSS
127 113 31 37
AB6
*CUT
128 114 30 36
AB7
IOVDD
129 35
VSS
VSS
130
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
34
COREVDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
COREVDD
VSS
RESET#
WE1#
WE0#
RD/WR#
CS#
VSS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
COREVDD
CLKI
IOVDD
XTAL1
XTAL0
VSS
AB16
AB15
AB14
AB13
AB12
AB11
AB10
AB9
AB8
IOVDD
VSS