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Page 148 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
bit 1 GPIO1 Pin IO Status
When GPIO1 is not used as a LCD signal and GPIO1 is configured as an output, writing a
1 to this bit drives GPIO1 high and writing a 0 to this bit drives GPIO1 low.
When GPIO1 is not used as a LCD signal and GPIO1 is configured as an input, a read
from this bit returns the status of GPIO1.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11) and a 1 is written to this bit, the
D-TFD signal YSCL signal is enabled.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11) and a 0 is written to this bit, the
D-TFD signal YSCL signal is forced low.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10) and a 1 is written to this bit,
the HR-TFT signal CLS signal is enabled.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10) and a 0 is written to this bit,
the HR-TFT signal CLS signal is forced low.
When a TFT Type 2 panel is enabled (REG[C5h] bits 1:0 = 01) and a 1 is written to this
bit, the AP signal is enabled.
When a TFT Type 2 panel is enabled (REG[C5h] bits 1:0 = 01) and a 0 is written to this
bit, the AP signal is forced low.
When a TFT Type 3 panel is enabled (REG[C5h] bits 1:0 = 10) and a 1 is written to this
bit, the OE signal is enabled.
When a TFT Type 3 panel is enabled (REG[C5h] bits 1:0 = 10) and a 0 is written to this
bit, the OE signal is forced low.
bit 0 GPIO0 Pin IO Status
When GPIO1 is not used as a LCD signal and GPIO0 is configured as an output, writing a
1 to this bit drives GPIO0 high and writing a 0 to this bit drives GPIO0 low.
When GPIO1 is not used as a LCD signal and GPIO0 is configured as an input, a read
from this bit returns the status of GPIO0.
When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11) writing to this bit has no effect.
When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10) writing to this bit has no
effect.
When a TFT Type 2 panel is enabled (REG[C5h] bits 1:0 = 01) writing to this bit has no
effect.
When a TFT Type 3 panel is enabled (REG[C5h] bits 1:0 = 10) writing to this bit has no
effect.