Filter
Top Products
Epson Research and Development Page 145
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
8.3.8 General IO Pins Registers
Note
If CNF3 = 0 at RESET#, then all GPIO pins are configured as outputs only and this reg-
ister has no effect. This case allows the GPIO pins to be used by the HR-TFT/D-TFD
panel interfaces. For a summary of GPIO usage for HR-TFT/D-TFD, see Table 4-10:
“LCD Interface Pin Mapping,” on page 40.
Note
The input functions of the GPIO pins are not enabled until REG[A9h] bit 7 is set to 1.
bit 6 GPIO6 Pin IO Configuration
When this bit = 0 (default), GPIO6 is configured as an input pin.
When this bit = 1, GPIO6 is configured as an output pin.
bit 5 GPIO5 Pin IO Configuration
When this bit = 0 (default), GPIO5 is configured as an input pin.
When this bit = 1, GPIO5 is configured as an output pin.
bit 4 GPIO4 Pin IO Configuration
When this bit = 0 (default), GPIO4 is configured as an input pin.
When this bit = 1, GPIO4 is configured as an output pin.
bit 3 GPIO3 Pin IO Configuration
When this bit = 0 (default), GPIO3 is configured as an input pin.
When this bit = 1, GPIO3 is configured as an output pin.
bit 2 GPIO2 Pin IO Configuration
When this bit = 0 (default), GPIO2 is configured as an input pin.
When this bit = 1, GPIO2 is configured as an output pin.
bit 1 GPIO1 Pin IO Configuration
When this bit = 0 (default), GPIO1 is configured as an input pin.
When this bit = 1, GPIO1 is configured as an output pin.
bit 0 GPIO0 Pin IO Configuration
When this bit = 0 (default), GPIO0 is configured as an input pin.
When this bit = 1, GPIO0 is configured as an output pin.
General Purpose IO Pins Configuration Register 0
REG[A8h] Read/Write
n/a
GPIO6 Pin IO
Configuration
GPIO5 Pin IO
Configuration
GPIO4 Pin IO
Configuration
GPIO3 Pin IO
Configuration
GPIO2 Pin IO
Configuration
GPIO1 Pin IO
Configuration
GPIO0 Pin IO
Configuration
76543210