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Page 14 Epson Research and Development
Vancouver Design Center
S1D13708 Windows® CE 3.x Display Drivers
X39A-E-006-01 Issue Date: 01/11/14
Comments
• The display driver is CPU independent, allowing use of the driver for several Windows
CE Platform Builder supported platforms. The file s1dflat.cpp will require editing for
the correct values of PhysicalPortAddr, PhysicalVmemAddr, etc.
• If you are running the display driver on hardware other than the S5U13708B00C evalu-
ation board, you must ensure that your hardware provides the correct clock frequencies
for CLKI, CLKI2 and XTAL. 13708CFG defaults to 50MHz for both CLKI and CLKI2,
and 12MHz for XTAL.
If you run the S1D13708 with a single clock source, make sure your clock sources for
PCLK, BCLK, and MCLK are correctly set to use the correct clock input source. Also
ensure that you enable the clock dividers as required for different display hardware.
• If you are using 13708cfg.exe to produce multiple MODE tables, make sure you change
the Mode Number setting for each mode table you generate. The display driver supports
multiple mode tables, but only if each mode table has a unique mode number. For more
information on setting the mode number, see the 13708CFG User Manual, document
number X39A-B-001-xx.
• The 13708CFG program assumes you are using the S5U13708B00C evaluation board,
and defaults the Panel Power control to GPIO0. 13708CFG allows you to change the
GPIO pin used to control panel power, or to disable the use of GPIO pins altogether. If
this is changed from the default, your driver will no longer be able to control panel
power on the S5U13708B00C evaluation board, and your panel may not be powered up
correctly.
• At this time, the driver has been tested on the x86 CPUs and have been run with Plat-
form Builder v3.00.