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Page 150 Epson Research and Development
Vancouver Design Center
S1D13708 Hardware Functional Specification
X39A-A-001-02 Issue Date: 02/03/07
8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse
Configuration Registers
Figure 8-2 PWM Clock/CV Pulse Block Diagram
Note
For further information on PWMCLK, see Section 7.1.4, “PWMCLK” on page 115.
bit 7 and bit 4 PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4)
These bits control the PWMOUT pin and PWM Clock circuitry as follows.
When PWMOUT is forced low or forced high it can be used as a general purpose output.
Note
The PWM Clock circuitry is disabled when Power Save Mode is enabled.
PWM Clock / CV Pulse Control Register
REG[B0h] Read/Write
PWM Clock
Force High
n/a
PWM Clock
Enable
CV Pulse
Force High
CV Pulse
Burst Status
(RO)
CV Pulse
Burst Start
CV Pulse
Enable
7 6 543210
Table 8-15: PWM Clock Control
Bit 7 Bit 4 Result
01
PWM Clock circuitry enabled
(controlled by REG[B1h] and REG[B3h])
0 0 PWMOUT forced low
1 x PWMOUT forced high
x = don’t care
PWM Clock
Divider
PWM Duty Cycle
Modulation
to PWMOUT
PWMCLK
Divided
Clock
Clock Source / 2
m
m = PWM Clock Divide Select value
Duty = n / 256
n = PWM Clock Duty Cycle
frequency =
Clock Source / (2
m
X 256)
CV Pulse Burst
Generation
y-pulse burst
PWM Clock Force High
frequency =
Clock Source / (2
x
X 2)
CV Pulse
Divider
Divided
Clock
Clock Source / 2
x
x = CV Pulse Divide Select value
y = Burst Length value
to CVOUT
CV Pulse Force High
PWMOUT Enable
CV Pulse Enable