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Page 14 Epson Research and Development
Vancouver Design Center
S1D13708 Interfacing to the Motorola MPC821 Microprocessor
X39A-G-009-01 Issue Date: 01/11/06
3.2 Host Bus Interface Signals
The Host Bus Interface requires the following signals.
• CLKI is a clock input which is required by the S1D13708 Host Bus Interface as a source
for its internal bus and memory clocks. This clock is typically driven by the host CPU
system clock. For this example, SYSCLK from the Motorola MPC821 is used for CLKI.
• The address inputs AB[16:0], and the data bus DB[15:0], connect directly to the
MPC821 address (A[15:31]) and data bus (D[0:15]), respectively. CNF4 must be set to
select big endian mode.
• Chip Select (CS#) must be driven low by CS4
whenever the S1D13708 is accessed by
the Motorola MPC821.
• M/R# (memory/register) selects between memory or register accesses. This signal may
be connected to an address line, allowing system address A14 to be connected to the
M/R# line.
• WE0# connects to WE1
(the low byte enable signal from the MPC821) and must be
driven low when the MPC821 is writing the low byte to the S1D13708.
• WE1# connects to WE0
(the high byte enable signal from the MPC821) and must be
driven low when the MPC821 is writing the high byte to the S1D13708.
• RD# and RD/WR# are read enables for the low-order and high-order bytes, respectively.
Both signals are driven low by OE
when the Motorola MPC821 is reading data from the
S1D13708.
• WAIT# connects to TA
and is a signal which is output from the S1D13708 which indi-
cates the MPC821 must wait until data is ready (read cycle) or accepted (write cycle) on
the host bus. Since MPC821 accesses to the S1D13708 may occur asynchronously to the
display update, it is possible that contention may occur in accessing the S1D13708
internal registers and/or display buffer. The WAIT# line resolves these contentions by
forcing the host to wait until the resource arbitration is complete.
• The Bus Status (BS#) signal is not used in this implementation of the MPC821 interface
using the Generic #1 Host Bus Interface. This pin must be tied high (connected to
IO V
DD
).