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Epson Research and Development Page 15
Vancouver Design Center
Interfacing to the Motorola RedCap2 S1D13708
Issue Date: 01/11/06 X39A-G-014-01
4.3 S1D13708 Hardware Configuration
The S1D13708 uses CNF7 through CNF0 to allow selection of the bus mode and other
configuration data on the rising edge of RESET#. For details on configuration, refer to the
S1D13708 Hardware Functional Specification, document number X39A-A-001-xx.
The following table shows the configuration required for this implementation of a
S1D13708 to Motorola REDCAP2 microprocessor.
4.4 Register/Memory Mapping
The S1D13708 is a memory mapped device. The S1D13708 uses two 128K byte blocks
which are selected using A17 from the REDCAP2 bus (A17 is connected to the S1D13708
M/R# pin). The internal registers occupy the first 128K byte block and the 80K byte display
buffer occupies the second 128K byte block. In this example, the S1D13708 internal
registers are accessed starting at address 4100 0000h and the display buffer is accessed
starting at address 4102 0000h.
Each Chip Select on the REDCAP2 is allocated a 16M byte block. However, the S1D13708
only needs a 256K byte block of memory to accommodate its register set and 80K byte
display buffer. For this reason, only address bits A[17:0] are used while A[21:18] are
ignored. The S1D13708’s memory and register are aliased every 256K bytes in the 16M
byte CS1 address space.
Note
If aliasing is not desirable, the upper addresses must be fully decoded.
Table 4-2: Summary of Power-On/Reset Options
S1D13708
Pin Name
state of this pin at rising edge of RESET# is used to configure:(1/0)
10
CNF[4, 2:0]
1101 = REDCAP2 Big Endian Host Bus Interface
CNF3 GPIO pins as inputs at power-on GPIO pins as HR-TFT/ D-TFD outputs
CNF5
WAIT# is active high
WAIT# is active low
CNF[7:6]
CLKI to BCLK divide select:
CNF7 CNF6 CLKI to BCLK Divide Ratio
0 0 1 : 1
0 1 2 : 1
1 0 3 : 1
114 : 1
= configuration for REDCAP2 microprocessor