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Epson Research and Development Page 131
Vancouver Design Center
Hardware Functional Specification S1D13708
Issue Date: 02/03/07 X39A-A-001-02
bits 9-0 FPLINE Pulse Start Position Bits [9:0]
These bits specify the start position of the horizontal sync signal, in 1 pixel resolution.
FPLINE Pulse Start Position in pixels = [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1]
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
bit 7 FPFRAME Pulse Polarity
This bit selects the polarity of the vertical sync signal. For most passive panels this bit
should be set to 1. For TFT panels this bit is set according to the vertical sync signal
required by the panel, typically FPFRAME, SPS or DY, depending on the panel type.
When this bit = 0, the vertical sync signal is active low.
When this bit = 1, the vertical sync signal is active high.
bits 2-0 FPFRAME Pulse Width Bits [2:0]
These bits specify the width of the panel vertical sync signal, in 1 line resolution. The ver-
tical sync signal is typically FPFRAME, SPS or DY, depending on the panel type.
FPFRAME Pulse Width in number of lines = (REG[24h] bits 2:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, “Display Inter-
face” on page 68.
FPLINE Pulse Start Position Register 0
REG[22h] Read/Write
FPLINE Pulse Start Position Bits 7-0
76543210
FPLINE Pulse Start Position Register 1
REG[23h] Read/Write
n/a
FPLINE Pulse Start Position
Bits 9-8
7 6 5 4 3 210
FPFRAME Pulse Width Register
REG[24h] Read/Write
FPFRAME
Pulse Polarity
n/a FPFRAME Pulse Width Bits 2-0
7 6 5 4 3210